arete_arix System 3000 Memory Module free download

File name System_3000_Memory_Module.pdf

1. Memory Module The memory module is the high speed system memory for the System 3000. It has on- board 32 bit error detection and correction (EDAC), refresh logic, and partial write logic. There are two interleaved arrays which can read, write, partial write, and refresh independently. This is accomplished by interleaving on address bit 2 so that even and odd four byte addresses go to opposite arrays. Because read operations return 8 bytes of data, they require both arrays to work together. Each array contains four 39 bit wide banks. The 39 bits include 32 bits of data and 7 check bits. Depopulated options of the module are possible by stuffing one, two, or all four of the banks in each array. This yields an 8, 16, or 32 megabyte memory module. The memory chips used are 1 megabit dynamic rams (1 Mb DRAMs). When 4 megabit DRAMs become available, they may be used in the module with only jumper changes. The stuffing options will then be 32, 64, or 128 megabytes per module. The access time of the DRAMs used must be no more than 100 nanoseconds (nS). Nibble mode access and CAS before RAS refresh are the other requirements of the DRAM chips. The ZIP (zig-zag in-line package) style is used to save module space and make the arrays more compact so that the control lines will be shorter. The size of the data used by the memory module depends on the type of access. Write cycles use a 32 bit data word. Partial write cycles must be generated by the memory module's control logic if it detects a write of less than four bytes. Read cycles return 64 bits to the requester. Burst mode is available on a read cycle so that the memory module r.etums 16 or 32 bytes of data for one read request. Write and 8 byte read cycles last five 50 nsec system clock periods. Partial write cycles are nine clocks long. Refresh cycles take sire clock periods. The 16 and 32 byte reads take eight and 14 clock periods each, respectively. Parity is checked on input to the module and parity is generated on output. Status registers are readable by other modules in the system to determine the memory size of the module, find the address of an error, see if the memory module is in diagnostic mode, or various other module characteristics. Control registers are available so that other mooules may enable or disable the memory array, put the module into diagnostic mode, inhibit error correction, or other functions. 1.1 Memory Module Description 1.1.1 Memory Module System Bus Interface Command, address and data if applicable get clocked into the bus input registers every 50 nsec by the 20 MHz system clock. The slot identifier field is compared with the memory module's slot number to see if the command is meant for this memory module. If there is a match, the top five bits of the address are checked for equality to all ones or all zeroes. If the bits are all ones, the status or control registers are to be accessed. If the bits are all zeroes, the access is to the memory array. If the